(1) Field of the Invention
The present invention relates to a semiconductor memory device having a level converter. Particularly, the present invention relates to a semiconductor memory device having a level converter in which the potential levels of a pair of output signals complementary to each other supplied from the level converter are changed (i.e., inverted) in accordance with the potential level of the control signal supplied from the circuit for controlling an inversion or non-inversion of an address bit signal in accordance with data stored therein (e.g., a logic level of an address bit corresponding to a portion of a standard memory cell array having a defective memory cell thereamong).
(2) Description of the Related Art
Recently, in a semiconductor memory device comprising complementary MOS (CMOS) circuits, portions of the semiconductor memory device (e.g., address buffer circuits to which corresponding address bit signals are input) are constructed by a circuit comprising bipolar transistors (e.g., by a circuit including emitter coupled logic gates) to increase the operational speed of the memory device. This type of semiconductor memory device is generally called a "BiCMOS" memory device.
In this type of semiconductor memory device, level converters must be provided between the respective address buffer circuits including emitter coupled logic gates constituted by NPN type bipolar transistors and a decoder circuit constituted by MOS transistors, for example, to convert the logic amplitude (i.e., the potential difference between a high logic level and a low logic level) of the output signals supplied from each of the address buffer circuits to a value different from that of the above output signals (i.e., to a larger value needed for operating the decoder circuit constituted by MOS transistors).
Further, in this type of semiconductor memory device, control circuits are provided for controlling the inversion or non-inversion of a corresponding address bit signal in accordance with data stored therein (e.g., a logic level of corresponding address bit corresponding to a portion of a standard memory cell array having a defective memory cell therein).
Accordingly, a portion of the standard memory cell array corresponding to a predetermined address (e.g., a predetermined row address) is selected through the decoder circuit in accordance with the potential levels of the address bit signals supplied from each of the level converters, when at least one logic level of the input address bit signals does not coincide with that of the data stored in the corresponding control circuit. Further, a redundancy memory cell array is selected through a circuit for controlling a switch from the standard memory cell array to the redundancy memory cell array, instead of the portion of the standard memory cell array having the defective memory cell therein, when each logic level of the input address bit signals coincides with that of the data stored in the corresponding control circuit.
To attain the above-mentioned operation, in the conventional address buffer circuit used in this type of semiconductor memory device, the circuit configuration comprising emitter coupled logic gates connected in series is adopted, to which gates are input the corresponding address bit signal and the control signal supplied from the circuit for controlling the inversion or non-inversion of the address bit signal in accordance with data stored therein, so that the potential levels of a pair of signals output from the address buffer circuit may be changed (i.e., inverted) in accordance with the potential levels of the above address bit signal and the above control signal.
Nevertheless, in the address buffer circuit constituted by the emitter coupled logic gates connected in series, problems arise in that a margin for the power supply potential applied to the address buffer circuit is reduced, and thus it is impossible to obtain a sufficient logic amplitude (i.e., sufficient potential difference between the high and low logic levels) for the output signal supplied from the address buffer circuit, and further, the speed of operation of the level converters connected after the corresponding address buffer circuits is reduced.